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Course Description This course introduces the AMD Versal™ network on chip (NoC) to users familiar with other SoC architectures. Besides providing an overview of the major components in the Versal device, the course illustrates how the NoC can be configured to access DDR memory controllers and HBM memory controllers. The emphasis of this course is on: ▪ Enumerating the major components comprising the NoC architecture in the Versal adaptive SoC ▪ Implementing a basic Versal NoC design using the Vivado™ IP integrator ▪ Accessing the Versal NoC using the modular NoC flow ▪ Configuring the DDR memory controller for accessing DDR memory ▪ Configuring and tunning the NoC for efficient data movement Level – VER 2 Course Details ▪ 1 day ILT /9 or 2 sessions Course Part Number – VER-NOC Who Should Attend? – Hardware developers and system architects— whether migrating from existing AMD SoC devices or starting out with the Versal devices Prerequisites ▪ Any SoC or Versal adaptive SoC architecture course ▪ Familiarity with the Vivado™ Design Suite ▪ Familiarity with the Vitis™ Unified IDE Software Tools ▪ Vivado Design Suite 2025.1 ▪ Vitis Unified IDE 2025.1 Hardware ▪ Architecture: Versal adaptive SoCs After completing this comprehensive training, you will have the necessary skills to: ▪ Identify the major network on chip components in the AMD Versal architecture ▪ Include the necessary components to access the NoC from the PL ▪ Access the Versal NoC resources using the IP integrator and/or modular NoC flow ▪ Design with the NoC and integrated DDR memory controller ▪ Configure connection QoS for efficient data movement Course Outline ▪ Architecture Overview for Existing Users Introduces to students who already have familiarity with AMD SoC architectures the new and updated features found in the Versal devices. Also provides an overview of the Versal portfolio. {Lecture} ▪ NoC Introduction and Concepts Covers the reasons to use the

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